During the fabrication of metal-oxide-semiconductors (MOS), a silicon substrate is typically divided into a plurality of active and isolation regions through an isolation process. A thin gate oxide is subsequently grown on an upper surface of the substrate and over the active regions. A plurality of gates are then formed over the gate oxide layer, so that each gate bridges the substrate between doped source/drain regions. The source/drain regions are consequently implanted with an impurity concentration sufficient to render them conductive.
MOS technology is greatly employed in the fabrication of non-volatile memory cells. There are many types of non-volatile memory, and they are known in the art as either read-only memory (ROM) or programmable-read-only memory (PROM). One type of MOS PROM is the flash memory EPROM (Erasable Programmable ROM). Typically flash EPROMs are comprised as an array of paired transistors: a select or access transistor and a storage transistor. Many flash EPROMS combine these two transistors into one device—a split-gate transistor with two gates sharing a single device channel. The control gate (CG) serves the function of the select or access transistor, while the floating gate (FG) serves as a storage device.
Non-volatile MOS PROMs can be fabricated using well-known technologies such as floating gate tunnel oxide, textured polysilicon, or EPROM-tunnel oxide, among others. Program and erase of the corresponding EPROM cell differ depending upon the type of technology employed. For example, a floating gate tunnel oxide EPROM transistor is programmed (electrons are moved into the floating gate) by biasing the control gate, and erased (electrons are moved out of the floating gate) by biasing the drain.
An example of a conventional stacked-gate flash memory cell is illustrated in FIG. 1, where on a semiconductor substrate 10, source and drain regions 72 and 74, respectively, are displaced laterally between a pair of field oxide regions 14. Field oxide regions 14 are formed by isolation techniques such as STI or LOCOS processes, and they provide electrical and physical separation between neighboring active regions. A tunnel oxide 24, a floating gate 26, an inter poly dielectric 76, and a control gate 36 form gate structure 100 on the semiconductor substrate 10.
In recent flash memory technologies, short program/erase times and low operating voltages are the main obstacles to overcome in order to realize high speed and density, and low power operation. Thus, it has become increasingly necessary to increase the capacitive coupling between the floating gate and the control gate of the memory cell, while simultaneously inhibiting electrons from escaping from the floating gate to the control gate. The control gate-to-floating gate capacitance, which affects the coupling ratio, depends upon the thickness of the inter poly dielectric (IPD) 76 between the two gates and the relative permittivity or dielectric constant, K, of the inter-poly dielectric.
Attempts have been made at progressively reducing the thickness of IPD to increase the floating capacitance, but the results have been limited. A thinner gate dielectric provides greater drive current and therefore increased speed. In addition, a thinner gate dielectric has greater control over the channel charge, thus reducing short channel effects. Nevertheless, thinner gate dielectrics pose greater problems of reliability, quality and manufacturing. Decreasing the thickness of IPD to increase the floating gate capacitance may cause serious leakage problems, which are fatal in the retention time of flash cell memories.
To reduce leakage current, silicon nitride has been used as the inter poly dielectric. The silicon nitride is sandwiched between two thin layers of silicon dioxide, forming a multi layered ONO structure. The ONO structure, however, does not permit aggressive scaling required for high speed and long retention flash memories. In devices with a 0.2-0.3 μm gate length, such as 256 Mb flash memory, the ONO IPD should be around 12 nm. To realize such a thin film, strict control of each dielectric layer is required. ONO inter poly dielectric poses scaling limitations, and so, the high gate leakage current and pin-hole density may not permit the use of silicon dioxide for CMOS beyond 70 nm.
In an effort to increase the coupling ratio without increasing the cell area and without reducing the dielectric thickness, gate dielectrics with a K greater than that of silicon dioxide have been introduced. Paraelectric materials have dielectric constants that are usually at least two orders of magnitude above that of silicon dioxide, but several problems limit their use as gate dielectrics. One such problem is oxygen diffusion. During high temperature processes associated with semiconductor fabrication, oxygen diffuses from the inter poly dielectric to the interface between the inter poly and the two polygates which sandwich it, forming an undesirable oxide layer that decreases the overall capacitance of the dielectric system and counteracts, therefore, the effect of the high dielectric constant paraelectric material.
Metal oxides have been proposed also as high K materials for flash memory applications. Metal oxides, in particular aluminum oxide (Al2O3) for which K is higher than 8, have a low leakage current to guarantee ten years of retention time and have high temperature endurance for process integration. However, because the deposited high dielectric metal oxides have non-stoichiometric composition, they have large electrical defects or traps in the bulk of the dielectric and also at the dielectric/semiconductor interface. These defects or traps enhance conduction through the dielectric and reduce the breakdown strength of the dielectric. Further, even though the pure Al2O3 films have resistivity higher than silicon nitride, the density of the leakage current is not low enough for flash devices.
Accordingly, there is a need for an improved Al2O3 oxide film with low gate leakage and low interface state density at the dielectric/Si interface, which could be used for flash technology or memory cell capacitors, such as DRAM. There is also a need for an improved Al2O3 oxide film that is stable at temperatures higher than 800° C. and that confers, therefore, low leakage current.